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QUAD UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART)
ST16C454 ST68C454
DESCRIPTION
The ST16C454 is a universal asynchronous receiver and transmitter (UART) with a dual foot print interface. The 454 is an enhanced UART with data rates up to 1.5Mbps and software compatible to ST16C450. Onboard status registers provide the user with error indications and operational status, modem interface control. System interrupts may be tailored to meet user requirements. An internal loop-back capability allows onboard diagnostics. The ST16C454 offer an additional 68 mode which allows easy integration with Motorola, and other popular microprocessors. The 454 combines the package interface modes of the ST16C454 and ST68C454 series on a single integrated chip.
PLCC Package
INTSEL -CDD 61
-CDA
GND
VCC
RXD 63
RXA
68
67
66
65
64
-DSRA -CTSA -DTRA VCC -RTSA INTA -CSA TXA -IOW TXB -CSB INTB -RTSB GND -DTRB -CTSB -DSRB
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
62
9
8
7
6
5
4
3
2
1
-RID
-RIA
D7
D6
D5
D4
D3
D2
D1
D0
60 59 58 57 56 55 54
-DSRD -CTSD -DTRD GND -RTSD INTD -CSD TXD -IOR TXC -CSC INTC -RTSC VCC -DTRC -CTSC -DSRC
ST16C454CJ68 16 MODE
53 52 51 50 49 48 47 46 45 44
VCC
RXC
RESET
16/-68
XTAL1
XTAL2
* Software compatibility with the Industry Standard 16C450 * 1.5 Mbps transmit/receive operation (24MHz) * Independent transmit and receive control * Software selectable Baud Rate Generator * Modem control signals (-CTS, -RTS, -DSR, -DTR, -RI, -CD) * Programmable character lengths (5, 6, 7, 8) * Even, odd, or no parity bit generation and detection * Internal loop-back diagnostics * TTL compatible inputs, outputs * Low power
68
67
66
65
64
63
62
-DSRA -CTSA -DTRA VCC -RTSA -IRQ -CS TXA R/-W TXB A3 N.C. -RTSB GND -DTRB
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
61 60 59 58 57 56 55 54
9
8
7
6
5
4
3
2
1
-CDD
-CDA
GND
VCC
RXD
RXA
-RID
-RIA
N.C.
D7
D6
D5
D4
D3
D2
D1
D0
-CDC
-CDB
RXB
A2
A1
A0
GND
-RIC
-RIB
N.C.
N.C.
FEATURES
-DSRD -CTSD -DTRD GND -RTSD N.C. N.C. TXD N.C. TXC A4 N.C. -RTSC VCC -DTRC -CTSC -DSRC
ST16C454CJ68 68 MODE
53 52 51 50 49 48 47 46 45 44
ORDERING INFORMATION
Part number
-CTSB -DSRB
ST16C454CJ68 ST16C454IJ68
68 68
VCC
RXC
16/-68
-RESET
XTAL1
XTAL2
Rev. 3.20 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 * (510) 668-7000 * FAX (510) 668-7017
-CDC
-CDB
RXB
A2
A1
A0
GND
-RIC
-RIB
N.C.
N.C.
Pins Package
PLCC PLCC
Operating temperature
0 C to + 70 C -40 C to + 85 C
ST16C454/68C454
Figure 2, Block Diagram 16 Mode
D0-D7 -IOR -IOW RESET
Data bus & Control Logic
Transmit Holding Registers
Transmit Shift Register
TX A-D
Inter Connect Bus Lines & Control signals
A0-A2 -CS A-D
Receive Holding Registers
Receive Shift Register
Register Select Logic
RX A-D
INT A-D INTSEL
Interrupt Control Logic
-DTR A-D -RTS A-D Clock & Baud Rate Generator XTAL1 XTAL2 Modem Control Logic -CTS A-D -RI A-D -CD A-D -DSR A-D
Rev. 3.20
2
ST16C454/68C454
Figure 3, Block Diagram 68 Mode
D0-D7 R/-W -RESET
Data bus & Control Logic
Transmit Holding Registers
Transmit Shift Register
TX A-D
A0-A4 -CS
Inter Connect Bus Lines & Control signals
Receive Holding Registers
Receive Shift Register
Register Select Logic
RX A-D
-IRQ
Interrupt Control Logic
-DTR A-D -RTS A-D Modem Control Logic -CTS A-D -RI A-D -CD A-D -DSR A-D
XTAL1 XTAL2
Rev. 3.20
3
Clock & Baud Rate Generator
ST16C454/68C454
SYMBOL DESCRIPTION
Symbol 16/-68 Pin 31 Signal type I Pin Description 16/68 Interface Type Select (input with internal pull-up). - This input provides the 16 (Intel) or 68 (Motorola) bus interface type select. The functions of -IOR, -IOW, INT A-D, and -CS A-D are reassigned with the logical state of this pin. When this pin is a logic 1, the 16 mode interface ST16C454 is selected. When this pin is a logic 0, the 68 mode interface (ST68C454) is selected. When this pin is a logic 0, -IOW is re-assigned to R/-W, RESET is re-assigned to -RESET, -IOR is not used, and INT A-D(s) are connected in a WIRE-OR configuration. The WIRE-OR outputs are connected internally to the open source IRQ signal output. Address-0 Select Bit. Internal registers address selection in 16 and 68 modes. Address-1 Select Bit. Internal registers address selection in 16 and 68 modes. Address-2 Select Bit. - Internal registers address selection in 16 and 68 modes. Address 3-4 Select Bits. - When the 68 mode is selected, these pins are used to address or select individual UARTs (providing CS is a logic 0). In the 16 mode, these pins are reassigned as chip selects, see -CSB and -CSC. Chip Select. (active low) - In the 68 mode, this pin functions as a multiple channel chip enable. In this case, all four UARTs (A-D) are enabled when the -CS pin is a logic 0. An individual UART channel is selected by the data contents of address bits A3-A4. When the 16 mode is selected, this pin functions as -CSA, see definition under -CS A-B. Chip Select A, B, C, D (active low) - This function is associated with the 16 mode only, and for individual channels, A through D. When in 16 Mode, these pins enable data transfers between the user CPU and the ST16C454 for the channel(s) addressed. Individual UART sections (A, B, C, D) are addressed by providing a logic 0 on the respective -CS A-D pin. When the 68 mode is selected, the functions of these pins are reassigned. 68 mode functions are described under the their respective name/pin headings.
A0 A1 A2 A3-A4
34 33 32 20,50
I I I I
-CS
16
I
-CS A-B -CS C-D
16,20 50,54
I
Rev. 3.20
4
ST16C454/68C454
SYMBOL DESCRIPTION
Symbol D0-D2 D3-D7 Pin 66-68 1-5 Signal type I/O Pin Description
Data Bus (Bi-directional) - These pins are the eight bit, three state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. Signal and power ground. Interrupt A, B, C, D (active high) - This function is associated with the 16 mode only. These pins provide individual channel interrupts, INT A-D. INT A-D are enabled when MCR bit-3 is set to a logic 1, interrupts are enabled in the interrupt enable register (IER), and when an interrupt condition exists. Interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, or when a modem status flag is detected. When the 68 mode is selected, the functions of these pins are reassigned. 68 mode functions are described under the their respective name/pin headings. Interrupt Select. (active high, with internal pull-down) - This function is associated with the 16 mode only. When the 16 mode is selected, this pin can be used in conjunction with MCR bit-3 to enable or disable the three state interrupts, INT A-D or override MCR bit-3 and force continuous interrupts. Interrupt outputs are enabled continuously by making this pin a logic 1. Making this pin a logic 0 allows MCR bit-3 to control the three state interrupt output. In this mode, MCR bit-3 is set to a logic 1 to enable the three state outputs. This pin is disabled in the 68 mode. Read strobe. (active low Strobe) - This function is associated with the 16 mode only. A logic 0 transition on this pin will load the contents of an Internal register defined by address bits A0-A2 onto the ST16C454 data bus (D0-D7) for access by an external CPU. This pin is disabled in the 68 mode. Write strobe. (active low strobe) - This function is associated with the 16 mode only. A logic 0 transition on this pin will transfer the contents of the data bus (D0-D7) from the external CPU to an internal register that is defined by address bits A0-A2. When the 16 mode is selected, this pin functions as R/-W, see definition
GND GND INT A-B INT C-D
6,23 40,57 15,21 49,55
Pwr O
INTSEL
65
I
-IOR
52
I
-IOW
18
I
Rev. 3.20
5
ST16C454/68C454
SYMBOL DESCRIPTION
Symbol Pin Signal type under R/-W. -IRQ 15 O Interrupt Request or Interrupt A - This function is associated with the 68 mode only. In the 68 mode, interrupts from UART channels A-D are WIRE-ORed internally to function as a single IRQ interrupt. This pin transitions to a logic 0 (if enabled by the interrupt enable register) whenever a UART channel(s) requires service. Individual channel interrupt status can be determined by addressing each channel through its associated internal register, using CS and A3-A4. In the 68 mode an external pull-up resistor must be connected between this pin and VCC. The function of this pin changes to INTA when operating in the 16 mode, see definition under INTA. Reset. - In the 16 mode a logic 1 on this pin will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. (See ST16C454 External Reset Conditions for initialization details.) When 16/-68 is a logic 0 (68 mode), this pin functions similarly but, as an inverted reset interface signal, -RESET. Read/Write Strobe (active low) - This function is associated with the 68 mode only. This pin provides the combined functions for Read or Write strobes. A logic 1 to 0 transition transfers the contents of the CPU data bus (D0-D7) to the register selected by -CS and A0-A4. Similarly a logic 0 to 1 transition places the contents of a 454 register selected by -CS and A0-A4 on the data bus, D0-D7, for transfer to an external CPU. Power supply inputs. Crystal or External Clock Input - Functions as a crystal input or as an external clock input. A crystal can be connected between this pin and XTAL2 to form an internal oscillator circuit (see figure 8). Alternatively, an external clock can be connected to this pin to provide custom data rates (see Baud Rate Generator Programming). Output of the Crystal Oscillator or Buffered Clock - (See also XTAL1). Crystal oscillator output or buffered clock output. Pin Description
-RESET RESET
37
I
R/-W
18
I
VCC VCC XTAL1
13 47,64 35
I I
XTAL2
36
O
Rev. 3.20
6
ST16C454/68C454
SYMBOL DESCRIPTION
Symbol -CD A-B -CD C-D Pin 9,27 43,61 Signal type I Pin Description
Carrier Detect (active low) - These inputs are associated with individual UART channels A through D. A logic 0 on this pin indicates that a carrier has been detected by the modem for that channel. Clear to Send (active low) - These inputs are associated with individual UART channels, A through D. A logic 0 on the -CTS pin indicates the modem or data set is ready to accept transmit data from the 454. Status can be tested by reading MSR bit-4. Data Set Ready (active low) - These inputs are associated with individual UART channels, A through D. A logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the UART. This pin has no effect on the UARTs transmit or receive operation. This pin has no effect on the UARTs transmit or receive operation. Data Terminal Ready (active low) - These inputs are associated with individual UART channels, A through D. A logic 0 on this pin indicates that the 454 is powered-on and ready. This pin can be controlled via the modem control register. Writing a logic 1 to MCR bit-0 will set the -DTR output to logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to MCR bit-0. This pin has no effect on the UARTs transmit or receive operation. Ring Indicator (active low) - These inputs are associated with individual UART channels, A through D. A logic 0 on this pin indicates the modem has received a ringing signal from the telephone line. A logic 1 transition on this input pin will generate an interrupt. Request to Send (active low) - These outputs are associated with individual UART channels, A through D. A logic 0 on the -RTS pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the modem control register (MCR bit-1) will set this pin to a logic 0 indicating data is available. After a reset this pin
-CTS A-B -CTS C-D
11,25 45,59
I
-DSR A-B -DSR C-D
10,26 44,60
I
-DTR A-B -DTR C-D
12,24 46,58
O
-RI A-B -RI C-D
8,28 42,62
I
-RTS A-B -RTS C-D
14,22 48,56
O
Rev. 3.20
7
ST16C454/68C454
SYMBOL DESCRIPTION
Symbol Pin Signal type Pin Description will be set to a logic 1. This pin has no effect on the UARTs transmit or receive operation. RX A-B RX C-D 7,29 41,63 I Receive Data Input RX A-D. - These inputs are associated with individual serial channel data to the ST16C454. The RX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the RX input pin is disabled and TX data is internally connected to the UART RX Input, internally. Transmit Data - These outputs are associated with individual serial transmit channel data from the 454. The TX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the TX input pin is disabled and TX data is internally connected to the UART RX Input.
TX A-B TX C-D
17,19 51,53
O
Rev. 3.20
8
ST16C454/68C454
GENERAL DESCRIPTION The 454 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). Data integrity is insured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip. The ST16C454 represents such an integration with greatly enhanced features. The 454 is fabricated with an advanced CMOS process to achieve low drain power and high speed requirements. The 454 combines the package interface modes of the ST16C454 and ST68C454 series on a single integrated chip. The 16 mode interface is designed to operate with the Intel type of microprocessor bus while the 68 mode is intended to operate with Motorola, and other popular microprocessors. The 454 is capable of operation to 1.5Mbps with a 24 MHz crystal or external clock input. With a crystal of 14.7464 MHz, the user can select data rates up to 921.6Kbps. The rich feature set of the 454 is available through internal registers. Selectable TX and RX baud rates, modem interface controls. In the 16 mode INTSEL and MCR bit-3 can be configured to provide a software controlled or continuous interrupt capability. FUNCTIONAL DESCRIPTIONS Interface Options Two user interface modes are selectable for the 454 package. These interface modes are designated as the 16 mode and the 68 mode. This nomenclature corresponds to the early ST16C454 and ST68C454 package interfaces respectively. Rev. 3.20
9
The 16 Mode Interface The 16 mode configures the package interface pins for connection as a standard 16 series (Intel) device and operates similar to the standard CPU interface available on the ST16C454. In the 16 mode (pin 16/-68 logic 1) each UART is selected with individual chip select (-CSx) pins as shown in Table 2 below. Table 2, SERIAL PORT CHANNEL SELECTION GUIDE, 16 MODE INTERFACE -CSA 1 0 1 1 1 -CSB 1 1 0 1 1 -CSC 1 1 1 0 1 -CSD 1 1 1 1 0 UART CHANNEL None A B C D
The 68 Mode Interface The 68 mode configures the package interface pins for connection with Motorola, and other popular microprocessor bus types. The interface operates similar to the ST68C454. In this mode the 454 decodes two additional addresses, A3-A4 to select one of the four UART ports. The A3-A4 address decode function is used only when in the 68 mode (16/-68 logic 0), and is shown in Table 3 below. Table 3, SERIAL PORT CHANNEL SELECTION GUIDE, 68 MODE INTERFACE -CS 1 0 0 0 0 A4 N/A 0 0 1 1 A3 N/A 0 1 0 1 UART CHANNEL None A B C D
ST16C454/68C454
Internal Registers The 454 provides 12 internal registers for monitoring and control. These resisters are shown in Table 4 below. These registers are similar to those already available in the standard 16C450. These registers function as data holding registers (THR/RHR), inter-
rupt status and control registers (IER/ISR), line status and control registers (LCR/LSR), modem status and control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a user assessable scratchpad register (SPR). Register functions are more fully described in the following paragraphs.
Table 4, INTERNAL REGISTER DECODE A2 A1 A0 READ MODE WRITE MODE
General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR): 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Receive Holding Register Interrupt Status Register Line Status Register Modem Status Register Scratchpad Register Transmit Holding Register Interrupt Enable Register Line Control Register Modem Control Register Scratchpad Register
Baud Rate Register Set (DLL/DLM): Note *2 0 0 0 0 0 1 LSB of Divisor Latch MSB of Divisor Latch LSB of Divisor Latch MSB of Divisor Latch
Note *2: These registers are accessible only when LCR bit-7 is set to a logic 1.
Rev. 3.20
10
ST16C454/68C454
Programmable Baud Rate Generator The 454 supports high speed modem technologies that have increased input data rates by employing data compression schemes. For example a 33.6Kbps modem that employs data compression may require a 115.2Kbps input data rate. A 128.0Kbps ISDN modem that supports data compression may need an input data rate of 460.8Kbps. The 454 can support a standard data rate of 921.6Kbps. Single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel control. The programmable Baud Rate Generator is capable of accepting an input clock up to 24 MHz, as required for supporting a 1.5Mbps data rate. The 454 can be configured for internal or external clock operation. For internal clock oscillator operation, an industry standard microprocessor crystal (parallel resonant/ 22-33 pF load) is connected externally between the XTAL1 and XTAL2 pins (see figure 8).
Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates. (see Baud Rate Generator Programming). The generator divides the input 16X clock by any divisor from 1 to 216 -1. The 454 divides the basic crystal or external clock by 16. Further division of this 16X clock provides two table rates to support low and high data rate applications using the same system design. Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate generator. Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired final baud rate. The example in Table 5 below, shows the two selectable baud rate tables available when using a 1.8432MHz or 7.3728 MHz crystal.
Output Output User Baud Rate Baud Rate 16 x Clock (1.8432 MHz (7.3728 MHz Divisor Clock) Clock) (Decimal) 50 300 600 1200 2400 4800 9600 19.2k 38.4k 57.6k 115.2k 200 1200 2400 4800 9600 19.2K 38.4k 76.8k 153.6k 230.4k 460.8k 2304 384 192 96 48 24 12 6 3 2 1
User 16 x Clock Divisor (HEX) 900 180 C0 60 30 18 0C 06 03 02 01
DLM Program Value (HEX) 09 01 00 00 00 00 00 00 00 00 00
DLL Program Value (HEX) 00 80 C0 60 30 18 0C 06 03 02 01
Rev. 3.20
11
ST16C454/68C454
Figure 8, Crystal oscillator connection
Loop-back Mode The internal loop-back capability allows onboard diagnostics. In the loop-back mode the normal modem interface pins are disconnected and reconfigured for loop-back internally. MCR register bits 0-3 are used for controlling loop-back diagnostic testing. In the loop-back mode OP1 and OP2 in the MCR register (bits 3/2) control the modem -RI and -CD inputs respectively. MCR signals -DTR and -RTS (bits 0-1) are used to control the modem -CTS and -DSR inputs respectively. The transmitter output (TX) and the receiver input (RX) are disconnected from their associated interface pins, and instead are connected together internally (See Figure 12). The -CTS, -DSR, CD, and -RI are disconnected from their normal modem control inputs pins, and instead are connected internally to -DTR, -RTS, -OP1 and -OP2. Loop-back test data is entered into the transmit holding register via the user data bus interface, D0-D7. The transmit UART serializes the data and passes the serial data to the receive UART via the internal loop-back connection. The receive UART converts the serial data back into parallel data that is then made available at the user data interface, D0-D7. The user optionally compares the received data to the initial transmitted data for verifying error free operation of the UART TX/RX circuits. In this mode, the receiver and transmitter interrupts are fully operational. The Modem Control Interrupts are also operational. However, the interrupts can only be read using lower four bits of the Modem Control Register (MCR bits 0-3) instead of the four Modem Status Register bits 4-7. The interrupts are still controlled by the IER.
XTAL1
X1 1.8432 MHz C1 22pF C2 33pF
Rev. 3.20
12
XTAL2
ST16C454/68C454
Figure 12, INTERNAL LOOP-BACK MODE DIAGRAM
Receive Holding Registers I n te r C o n n e c t B u s L in e s & C o n tr o l s ig n a ls Register Select Logic
Receive Shift Register
MCR Bit-4=1 RX A-D -RTS A-D -CD A-D -DTR A-D Modem Control Logic -RI A-D (-OP1 A-D) -DSR A-D (-OP2 A-D) -CTS A-D
13
D0-D7 -IOR,-IOW RESET
A0-A2 -CS A-D
INT A-D
XTAL1 XTAL2
Rev. 3.20
Clock & Baud Rate Generator
Interrupt Control Logic
Data bus & Control Logic
Transmit Holding Registers
Transmit Shift Register
TX A-D
ST16C454/68C454
REGISTER FUNCTIONAL DESCRIPTIONS The following table delineates the assigned bit functions for the fifteen 454 internal registers. The assigned bit functions are more fully defined in the following paragraphs. Table 6, ST16C454 INTERNAL REGISTERS
A2 A1 A0
Register [Default] Note *5
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
General Register Set
0 0 0 0 0 0 0 0 1 RHR[XX] THR[XX] IER[00] bit-7 bit-7 0 bit-6 bit-6 0 bit-5 bit-5 0 bit-4 bit-4 0 bit-3 bit-3 modem status interrupt INT priority bit-2 parity enable -OP2/ INTx enable framing error delta -CD bit-3 bit-2 bit-2 receive line status interrupt INT priority bit-1 stop bits -OP1 bit-1 bit-1 transmit holding register INT priority bit-0 word length bit-1 -RTS bit-0 bit-0 receive holding register INT status word length bit-0 -DTR
0
1
0
ISR[01]
0
0
0
0
0
1
1
LCR[00]
divisor latch enable 0
set break 0
set parity 0
even parity loop back break interrupt CTS bit-4
1
0
0
MCR[00]
1
0
1
LSR[60]
0
trans. empty RI bit-6
trans. holding empty DSR bit-5
parity error delta -RI bit-2
overrun error delta -DSR bit-1
receive data ready delta -CTS bit-0
1 1
1 1
0 1
MSR[X0] SPR[FF]
CD bit-7
Special Register set: Note *2
0 0 0 0 0 1 DLL[XX] DLM[XX] bit-7 bit-15 bit-6 bit-14 bit-5 bit-13 bit-4 bit-12 bit-3 bit-11 bit-2 bit-10 bit-1 bit-9 bit-0 bit-8
Note *2: The Special register set is accessible only when LCR bit-7 is set to 1.
Rev. 3.20
14
ST16C454/68C454
Transmit (THR) and Receive (RHR) Holding Registers The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to the THR, providing that the THR or TSR is empty. The THR empty flag in the LSR register will be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR. Note that a write operation can be performed when the transmit holding register empty flag is set. The serial receive section also contains an 8-bit Receive Holding Register, RHR. Receive data is removed from the 454 by reading the RHR register. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at 16x clock rate. After 7 1/2 clocks the start bit time should be shifted to the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. Receiver status codes will be posted in the LSR. Interrupt Enable Register (IER) The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter empty, line status and modem status registers. These interrupts would normally be seen on the INT A-D output pins in the 16 mode, or on WIRE-OR IRQ output pin, in the 68 mode. IER BIT-0: This interrupt will be issued when the RHR is full, cleared when the RHR is empty. Logic 0 = Disable the receiver ready interrupt. (normal default condition) Logic 1 = Enable the receiver ready interrupt. IER BIT-1: This interrupt will be issued whenever the THR is empty and is associated with bit-1 in the LSR register. Logic 0 = Disable the transmitter empty interrupt. (normal default condition) Rev. 3.20
15
Logic 1 = Enable the transmitter empty interrupt. IER BIT-2: This interrupt will be issued whenever a fully assembled receive character is transferred from the RSR to the RHR, data ready, LSR bit-0. Logic 0 = Disable the receiver line status interrupt. (normal default condition) Logic 1 = Enable the receiver line status interrupt. IER BIT-3: Logic 0 = Disable the modem status register interrupt. (normal default condition) Logic 1 = Enable the modem status register interrupt. IER BIT 4-7: Not used - Initialized to a logic 0. Interrupt Status Register (ISR) The 454 provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced. No other interrupts are acknowledged until the pending interrupt is serviced. Whenever the interrupt status register is read, the interrupt status is cleared. However it should be noted that only the current pending interrupt is cleared by the read. A lower level interrupt may be seen after rereading the interrupt status bits. The Interrupt Source Table 7 (below) shows the data values (bit 0-5) for the four prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels:
ST16C454/68C454
Table 7, INTERRUPT SOURCE TABLE Priority Level 1 2 3 4 [ ISR BITS ] Bit-3 Bit-2 Bit-1 Bit-0 0 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 Source of the interrupt LSR (Receiver Line Status Register) RXRDY (Received Data Ready) TXRDY ( Transmitter Holding Register Empty) MSR (Modem Status Register)
ISR BIT-0: Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine. Logic 1 = No interrupt pending. (normal default condition) ISR BIT 1-3: (logic 0 or cleared is the default condition) These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (See Interrupt Source Table). ISR BIT 4-7: Not used - Initialized to a logic 0. Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. LCR BIT 0-1: (logic 0 or cleared is the default condition) These two bits specify the word length to be transmitted or received. BIT-1 0 0 1 1 BIT-0 0 1 0 1 Word length 5 6 7 8
LCR BIT-2: (logic 0 or cleared is the default condition) The length of stop bit is specified by this bit in conjunction with the programmed word length. BIT-2 Word length Stop bit length (Bit time(s)) 1 1-1/2 2
0 1 1
5,6,7,8 5 6,7,8
LCR BIT-3: Parity or no parity can be selected via this bit. Logic 0 = No parity. (normal default condition) Logic 1 = A parity bit is generated during the transmission, receiver checks the data and parity for transmission errors. LCR BIT-4: If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format. Logic 0 = ODD Parity is generated by forcing an odd number of logic 1s in the transmitted data. The receiver must be programmed to check the same format. (normal default condition) Logic 1 = EVEN Parity is generated by forcing an even the number of logic 1s in the transmitted. The receiver must be programmed to check the same format. LCR BIT-5: If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
Rev. 3.20
16
ST16C454/68C454
LCR BIT-5 = logic 0, parity is not forced. (normal default condition) LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. LCR Bit-5 X 0 0 1 1 LCR Bit-4 X 0 1 0 1 LCR Bit-3 0 1 1 1 1 Parity selection No parity Odd parity Even parity Force parity 1 Forced parity 0
MCR BIT-2: This bit is used in the Loop-back mode only. In the loop-back mode this bit is use to write the state of the modem -RI interface signal via -OP1. MCR BIT-3: (Used to control the modem -CD signal in the loop-back mode.) Logic 0 = Forces INT (A-D) outputs to the three state mode during the 16 mode. (normal default condition) In the Loop-back mode, sets -OP2 (-CD) internally to a logic 1. Logic 1 = Forces the INT (A-D) outputs to the active mode during the 16 mode. In the Loop-back mode, sets -OP2 (-CD) internally to a logic 0. MCR BIT-4: Logic 0 = Disable loop-back mode. (normal default condition) Logic 1 = Enable local loop-back mode (diagnostics). MCR BIT 5-7: Not used - Initialized to a logic 0. Line Status Register (LSR) This register provides the status of data transfers between. the 454 and the CPU. LSR BIT-0: Logic 0 = No data in receive holding register. (normal default condition) Logic 1 = Data has been received and is saved in the receive holding register. LSR BIT-1: Logic 0 = No overrun error. (normal default condition) Logic 1 = Overrun error. A data overrun error occurred in the receive shift register. This happens when additional data arrives while the RHR is full. In this case the previous data in the shift register is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into the RHR, therefore the data in the RHR is not corrupted by the error. LSR BIT-2: Logic 0 = No parity error. (normal default condition) Logic 1 = Parity error. The receive character does not have correct parity information and is suspect. In the RHR mode, this error is associated with the character
17
LCR BIT-6: When enabled the Break control bit causes a break condition to be transmitted (the TX output is forced to a logic 0 state). This condition exists until disabled by setting LCR bit-6 to a logic 0. Logic 0 = No TX break condition. (normal default condition) Logic 1 = Forces the transmitter output (TX) to a logic 0 for alerting the remote receiver to a line break condition. LCR BIT-7: Not used - Initialized to a logic 0. Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. MCR BIT-0: Logic 0 = Force -DTR output to a logic 1. (normal default condition) Logic 1 = Force -DTR output to a logic 0. MCR BIT-1: Logic 0 = Force -RTS output to a logic 1. (normal default condition) Logic 1 = Force -RTS output to a logic 0. Rev. 3.20
ST16C454/68C454
at the top of the RHR. LSR BIT-3: Logic 0 = No framing error. (normal default condition) Logic 1 = Framing error. The receive character did not have a valid stop bit(s). LSR BIT-4: Logic 0 = No break condition. (normal default condition) Logic 1 = The receiver received a break signal (RX was a logic 0 for one character frame time). LSR BIT-5: This bit indicates that the 454 is ready to accept new characters for transmission. This bit causes the 454 to issue an interrupt to the CPU when the transmit holding register is empty and the interrupt enable is set. Logic 0 = Transmit holding register is not empty. (normal default condition) Logic 1 = Transmit holding register is empty. LSR BIT-6: Logic 0 = Transmitter holding and shift registers are full. Logic 1 = Transmitter holding and shift registers are empty (normal default condition). LSR BIT-7: Not used - Initialized to a logic 0. Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device that the 454 is connected to. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state. These bits are set to a logic 0 whenever the CPU reads this register. MSR BIT-0: Logic 0 = No -CTS Change (normal default condition) Logic 1 = The -CTS input to the 454 has changed state since the last time it was read. A modem Status Interrupt will be generated. Rev. 3.20
18
MSR BIT-1: Logic 0 = No -DSR Change. (normal default condition) Logic 1 = The -DSR input to the 454 has changed state since the last time it was read. A modem Status Interrupt will be generated. MSR BIT-2: Logic 0 = No -RI Change. (normal default condition) Logic 1 = The -RI input to the 454 has changed from a logic 0 to a logic 1. A modem Status Interrupt will be generated. MSR BIT-3: Logic 0 = No -CD Change. (normal default condition) Logic 1 = Indicates that the -CD input to the has changed state since the last time it was read. A modem Status Interrupt will be generated. MSR BIT-4: -CTS (active high, logical 1). Normally MSR bit-4 bit is the compliment of the -CTS input. However in the loop-back mode, this bit is equivalent to the RTS bit in the MCR register. MSR BIT-5: DSR (active high, logical 1). Normally this bit is the compliment of the -DSR input. In the loop-back mode, this bit is equivalent to the DTR bit in the MCR register. MSR BIT-6: RI (active high, logical 1). Normally this bit is the compliment of the -RI input. In the loop-back mode this bit is equivalent to the OP1 bit in the MCR register. MSR BIT-7: CD (active high, logical 1). Normally this bit is the compliment of the -CD input. In the loop-back mode this bit is equivalent to the OP2 bit in the MCR register. Scratchpad Register (SPR) The ST16C454 provides a temporary data register to store 8 bits of user information.
ST16C454/68C454
ST16C454 EXTERNAL RESET CONDITIONS REGISTERS IER ISR LCR MCR LSR MSR RESET STATE IER BITS 0-7=0 ISR BIT-0=1, ISR BITS 1-7=0 LCR BITS 0-7=0 MCR BITS 0-7=0 LSR BITS 0-4=0, LSR BITS 5-6=1 LSR, BIT 7=0 MSR BITS 0-3=0, MSR BITS 4-7= input signals
SIGNALS TX A-D -RTS A-D -DTR A-D INT A-D
RESET STATE High High High Three-State
Rev. 3.20
19
ST16C454/68C454
AC ELECTRICAL CHARACTERISTICS
TA=0 - 70C (-40 - +85C for Industrial grade packages), Vcc=3.3 - 5.0 V 10% unless otherwise specified. Symbol Parameter Limits 3.3 Min Max 17 5 10 35 0 40 10 35 0 40 20 5 8 Limits 5.0 Min Max 17 0 10 25 0 30 35 10 25 0 30 15 5 24 Units Conditions
T1w,T2w T3w T6s T7d T7w T7h T9d T12d T12h T13d T13w T13h T15d T16s T16h T17d T18d T19d T20d T21d T22d T23d T24d T25d T26d T27d T28d T30s T30w T30h T30d T31d T31h T32s T32h T32d
Clock pulse duration Oscillator/Clock frequency Address setup time -IOR delay from chip select -IOR strobe width Chip select hold time from -IOR Read cycle delay Delay from -IOR to data Data disable time -IOW delay from chip select -IOW strobe width Chip select hold time from -IOW Write cycle delay Data setup time Data hold time Delay from -IOW to output Delay to set interrupt from MODEM input Delay to reset interrupt from -IOR Delay from stop to set interrupt Delay from -IOR to reset interrupt Delay from stop to interrupt Delay from initial INT reset to transmit start Delay from -IOW to reset interrupt Delay from stop to set -RxRdy Delay from -IOR to reset -RxRdy Delay from -IOW to set -TxRdy Delay from start to reset -TxRdy Address setup time Chip select strobe width Address hold time Read cycle delay Delay from -CS to data Data disable time Write strobe setup time Write strobe hold time Write cycle delay
35 25
25 15
50 40 40 1 45 45 24 45 1 45 45 8
40 35 35 1 40 40 24 40 1 40 40 8
ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Rclk ns ns Rclk ns Rclk ns ns Rclk ns ns ns ns ns ns ns ns ns
100 pF load 100 pF load 100 pF load 100 pF load
8
8
10 40 15 70 15 10 10 70
10 40 15 70 15 15 10 10 70
Rev. 3.20
20
ST16C454/68C454
AC ELECTRICAL CHARACTERISTICS
TA=0 - 70C (-40 - +85C for Industrial grade packages), Vcc=3.3 - 5.0 V 10% unless otherwise specified. Symbol Parameter Limits 3.3 Min Max 20 10 40 1 Limits 5.0 Min Max 15 10 40 1 Units Conditions
T33s T33h TR N
Data setup time Data hold time Reset pulse width Baud rate devisor
216-1
216-1
ns ns ns Rclk
Rev. 3.20
21
ST16C454/68C454
ABSOLUTE MAXIMUM RATINGS
Supply range Voltage at any pin Operating temperature Storage temperature Package dissipation 7 Volts GND - 0.3 V to VCC +0.3 V -40 C to +85 C -65 C to 150 C 500 mW
DC ELECTRICAL CHARACTERISTICS
TA=0 - 70C (-40 - +85C for Industrial grade packages), Vcc=3.3 - 5.0 V 10% unless otherwise specified. Symbol Parameter Limits 3.3 Min Max -0.3 2.4 -0.3 2.0 0.6 VCC 0.8 0.4 2.0 10 10 3 5 Limits 5.0 Min Max -0.5 3.0 -0.5 2.2 2.4 10 10 6 5 15 0.6 VCC 0.8 VCC 0.4 Units Conditions
VILCK VIHCK VIL VIH VOL VOL VOH VOH IIL ICL I CC CP RIN
Clock input low level Clock input high level Input low level Input high level Output low level on all outputs Output low level on all outputs Output high level Output high level Input leakage Clock leakage Avg power supply current Input capacitance Internal pull-up resistance
3
V V V V V V V V A A mA pF k
IOL= 5 mA IOL= 4 mA IOH= -5 mA IOH= -1 mA
Note: See the Symbol Description Table, for a listing of pins having internal pull-up resistors.
Rev. 3.20
22
ST16C454/68C454
A0-A4 T30s -CS T31h R/-W T31d D0-D7 8654-RD-1 T30w T30h T30d
General read timing in 68 mode
A0-A4 T30s -CS T32s R/-W T33h T33s D0-D7 8654-WD-1 T32h T30w T32d T30h
General write timing in 68 mode
Rev. 3.20
23
ST16C454/68C454
A0-A2 T6s -CS T7d -IOR T12d D0-D7
Valid Address
Active T7w Active T12h Data X552-RD-1 T7h T9d
General read timing in 16 mode
A0-A2 T6s -CS T13d -IOW
Valid Address
Active T13w Active T16s T16h Data X552-WD-1 T13h T15d
D0-D7
General write timing in 16 mode
Rev. 3.20
24
ST16C454/68C454
-IOW
Active T17d
-RTS -DTR
Change of state
Change of state
-CD -CTS -DSR T18d INT
Change of state
Change of state T18d
Active T19d
Active
Active
-IOR
Active
Active
Active T18d
-RI
Change of state X552-MD-1
Modem input/output timing
T2w EXTERNAL CLOCK T3w
T1w
X654-CK-1
External clock timing
Rev. 3.20
25
ST16C454/68C454
START BIT
DATA BITS (5-8) D0 D1 D2 D3 D4 D5 D6 D7
STOP BIT
RX
5 DATA BITS 6 DATA BITS 7 DATA BITS INT
PARITY BIT
NEXT DATA START BIT T20d Active T21d
-IOR
Active
16 BAUD RATE CLOCK
X552-RX-1
Receive timing
Rev. 3.20
26
ST16C454/68C454
START BIT
DATA BITS (5-8) D0 D1 D2 D3 D4 D5 D6 D7
STOP BIT
TX
5 DATA BITS 6 DATA BITS 7 DATA BITS INT T23d -IOW Active
PARITY BIT
NEXT DATA START BIT T22d Active Tx Ready T24d
Active
16 BAUD RATE CLOCK
X552-TX-1
Transmit timing
Rev. 3.20
27
ST16C454/68C454
Rev. 3.20
28
Package Dimensions
68 LEAD PLASTIC LEADED CHIP CARRIER (PLCC)
Rev. 1.00
D D1 45 x H2 2 1 68 B1 45 x H1 C Seating Plane A2
B D D1 D3 D2
e
R D3 A1 A
INCHES SYMBOL A A1 A2 B B1 C D D1 D2 D3 e H1 H2 R MIN 0.165 0.090 0.020 0.013 0.026 0.008 0.985 0.950 0.890 MAX 0.200 0.130 ---. 0.021 0.032 0.013 0.995 0.958 0.930
MILLIMETERS MIN 4.19 2.29 0.51 0.33 0.66 0.19 25.02 24.13 22.61 MAX 5.08 3.30 --- 0.53 0.81 0.32 25.27 24.33 23.62
0.800 typ. 0.050 BSC 0.042 0.042 0.025 0.056 0.048 0.045
20.32 typ. 1.27 BSC 1.07 1.07 0.64 1.42 1.22 1.14
Note: The control dimension is the inch column
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1994 EXAR Corporation Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

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